Delay stage-interweaved analog DLL/PLL
Delay stage-interweaved analog DLL/PLL
Delay-locked loop with binary-coupled capacitor
Delay-locked loop with binary-coupled capacitor
Delay-locked loop with binary-coupled capacitor
Delay-locked loop with binary-coupled capacitor
Delayed bitline leakage compensation circuit for memory devices
Delayed line for sense amplifier pulse
Delayed sense amplifier multiplexer isolation
Dense EPROM having serially coupled floating gate transistors
Deselect circuit
Desensitizing static random access memory (SRAM) to process...
Design for test to emulate a read with worse case test pattern
Design of provably correct storage arrays
Design structure for improving sensing margin of...
Design structure for in-system redundant array repair in...
Designing memory for testability to support scan capability...
Designs of reference cells for magnetic tunnel junction...
Destructive read type memory circuit, restoring circuit for...
Destructive read type memory circuit, restoring circuit for...