Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-05-07
2003-05-27
Mai, Son (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S185090
Reexamination Certificate
active
06570797
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention.
The present invention relates to semiconductor memory and in particular performing a read test on a nonvolatile memory cell.
2. Description of Related Art.
During a read operation of a nonvolatile EEPROM flash memory cell, the cell current will flow through two paths to ground. One path is through the source driver and the second path is through unselected erased cells. The second path is called herein a parasitic conduction path. The reference level of the memory sense amplifier circuit is dependent on the conductivity of the path from the source line to ground of a selected row of memory cells. Therefore, the more erased cells in the selected row, the higher the conductivity from the source line to ground. This is caused by the erased cells being on and providing a second path for the selected cell current to reach ground. The reference level of the memory sense amplifier will, therefore, be dependent upon the data pattern of the unselected cells on a selected word line during a read operation.
U.S. Pat. No. 5,717,652 (Ooishi) is directed to the testing time of a semiconductor memory device using a test mode to activate internal time period settings. In U.S. Pat. No. 5,784,314 (Sali et al.) a method is directed to setting the threshold voltage of a reference memory cell. U.S. Pat. No. 6,262,927B1 (Beigel et al.) is directed to a read test for a current saturation test device.
In
FIG. 1
is shown a portion of a flash memory array of prior art where memory cells M
0
, M
1
, Mm, Mm+1 and Mn are connected together with the same source line
10
. The source line
10
has a resistivity of approximately one hundred ohms per cell and is strapped with a metal source line
11
, which has a resistivity of approximately zero ohms per cell. A selected bit line
12
is connected to a sense amplifier
13
, where the memory cell Mm+1 is the selected cell. Cells M
0
, M
1
, Mm and Mn represent unselected cells that are connected to the source line
10
. The bit lines connected to the unselected cells, as represented by
14
, are connected to ground. When an unselected cell, such as cell M
1
, is in an erased state, the cell transistor is on and can provide a leakage path
15
for current to flow from the source of the selected cell to ground. Other cells connected to the common source line can also be in an erased state, providing additional leakage paths for the cell current to flow to ground. This requires the reference level
16
of the sense amplifier
13
to be set differently depending on the conductivity of the path from the source line to ground. Since the state of the unselected cells is hard to control for test purposes, testing a read operation to within satisfactory margins is difficult to do; and therefore, a test margin in chip production (CP) test is small.
To overcome problems test margin during CP test in the prior art a whole chip is first erased and then a memory cell is read to verify the erasure. Since all the cells on a word line are in an erase state, the conductivity of the source line to ground is high as a result of the large number of parasitic conduction paths through the erased unselected memory cells. The sense amplifier reference level is 'set lower as a result of the high conductivity of the source line to ground, which results in a lower test margin being guaranteed by the chip production test. To correct this problem a method is needed that produces a worse case condition so that adequate test margins can be established for a read test.
SUMMARY OF THE INVENTION
It is an objective of the present invention to establish a high effective impedance for each of the unselected memory cells between a bit line and a source line common with a memory cell being read.
It is also an objective of the present invention establish the high effective impedance of unselected memory cells between bit lines and a source line common with a memory cell being read regardless of the erase state of each unselected memory cell.
It is further an objective of the present invention to connect to a buffer amplifier the bit lines of unselected memory cells common to a source line and set the output of the buffer amplifier to high impedance when a memory cell connected to the source line is measured by a read operation.
It is still further an objective of the present invention that the buffer amplifier connected to bit lines have an output that is ground for normal read operations, a high impedance state to emulate a worse case impedance for test and a voltage Vcc for programming.
In the present invention bit lines of unselected cells of a flash memory that are connected to a common source line with a selected cell are connected to a tri-state buffer during a test read operation. When the tri-state buffer is used in a test read operation all unselected bit lines are connected to a high impedance which emulates all unselected cells being programmed and in an “off” state. This provides a worse case condition with which to read a selected cell with proper voltage margins to guarantee the read operation of the memory. Besides the high impedance output state for a test read, the tri-state buffer provides an output that is ground for normal read operations and a voltage Vcc for a programming operation.
The present invention provides a defined configuration to read test any memory array where unselected array bit are connected to ground through a source line. These memory arrays include flash, EEPROM, ROM and other nonvolatile arrays. A source line is usually a diffusion within a semiconductor substrate resulting in approximately one hundred ohms per cell that may be strapped with a metal line that is approximately zero ohms per cell. The strap is not physically connected to the diffused source line at every cell location and as a result in the prior art there is a voltage drop developed along the diffused source line depending upon the number of cells that are erased, or in an on state. This voltage drop in the prior art is a result of total current flowing in the source line from selected cells.
Effective cell current is dependent on source line voltage. The effective cell current is larger if the source line voltage is lower. During CP test all cells in the selected row are in an erase state, and the parasitic conduction path from the source line to ground will cause a lower source line voltage. However, not all cells are in an erase state in a real application. Therefore, the CP test will not be a worse case condition and less test margin will be guaranteed by the CP test.
The voltage on the source line is equal to the product of the total current I
T
of the selected cells and the resistance from the source line to ground R
T
. The resistance R
T
is the parallel combination of the on resistance of the source line driver R
S
and the resistance of the conduction path through all the erased cells R
C
. If all the cells on a source line are erased, then R
C
is the smallest and R
T
is also the smallest. This results in the source line being the smallest, which is a best test condition. In the present invention the path through the erased unselected cells is controlled off by a tri-state buffer. The tri-state buffer provides a very large impedance, which allows R
T
to be approximately equal to R
S
and produces a worse case condition.
REFERENCES:
patent: 5587946 (1996-12-01), Campardo et al.
patent: 5717652 (1998-02-01), Ooishi
patent: 5784314 (1998-07-01), Sali et al.
patent: 6243313 (2001-06-01), Sakamoto et al.
patent: 6262927 (2001-07-01), Beigel et al.
Ackerman Stephen B.
Mai Son
Saile George O.
Taiwan Semiconductor Manufacturing Company
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