Static information storage and retrieval – Read/write circuit – With shift register
Reexamination Certificate
2005-12-08
2009-02-10
Nguyen, Viet Q (Department: 2827)
Static information storage and retrieval
Read/write circuit
With shift register
C365S191000, C365S193000, C365S194000, C365S189080, C327S158000, C327S159000, C327S141000, C327S161000, C327S149000
Reexamination Certificate
active
07489568
ABSTRACT:
A methodology is disclosed that enables the delay stages of an analog delay locked loop (DLL) or phase locked loop (PLL) to be programmed according to the operating condition, which may depend on the frequency of the input reference clock. The resulting optimized delay stages allow for a broad frequency range of operation, fast locking time over a wide range of input clock frequencies, and a lower current consumption at high clock frequencies. Better performance is achieved by allowing the number of analog delay stages active during a given operation to be flexibly set. The deactivation or turning off of unused delay stages conserves power at higher frequencies. The high frequency range of operation is increased by using a flexible number of delay stages for various input clock frequencies. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
REFERENCES:
patent: 5610954 (1997-03-01), Miyashita et al.
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6166990 (2000-12-01), Ooishi et al.
patent: 6333660 (2001-12-01), Taguchi et al.
patent: 6385126 (2002-05-01), Jung et al.
patent: 6424193 (2002-07-01), Hwang
patent: 6677791 (2004-01-01), Okuda et al.
patent: 6937076 (2005-08-01), Gomm
patent: 7149145 (2006-12-01), Kim et al.
patent: 7242733 (2007-07-01), Iwata
patent: 7282972 (2007-10-01), Lin
John G. Maneatis, Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques, IEEE Journal, Nov. 1996, 1723-1732, vol. 31, No. 11.
Choi Dong Myung
Kim Kang Yong
Jones Day
Micro)n Technology, Inc.
Nguyen Viet Q
Pencoske Edward L.
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