Deselect circuit

Static information storage and retrieval – Read/write circuit – Precharge

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Details

365204, 36523003, 365233, G11C 700, G11C 800

Patent

active

052435725

ABSTRACT:
A deselect circuit (10) receiving a variable number of input signals which enables an output stage to generate a logic state signifying a deselect condition at a deselect output (12). The deselect circuit (10) operates synchronously having a clock signal (21) and inverted clock signal (22) to control internal timings. The deselect output (12) is preset to a logic state signifying a select condition prior to starting a deselect sequence, thus eliminating the need for circuitry to generate the select condition. The path for generating a deselect condition comprises a transmission gate which couples the inverted clock signal to a driver stage, a multiple input switch which couples the driver stage to a output stage, and the output stage which generates a logic state signifying a deselect condition at the deselect output (12). A sensing circuit is used to sense the select condition and enable a second driver stage to maintain the select condition.

REFERENCES:
patent: 4636991 (1987-01-01), Flannagan et al.
patent: 4658381 (1987-04-01), Reed et al.
patent: 4661931 (1987-04-01), Flannagan et al.
patent: 4698788 (1987-10-01), Flannagan et al.
patent: 4757215 (1988-07-01), Seo
patent: 4794570 (1988-12-01), Rose et al.
patent: 4881203 (1989-11-01), Watanabe et al.
patent: 4984201 (1991-01-01), Sato et al.
patent: 4984204 (1991-01-01), Sato et al.
patent: 5153459 (1992-10-01), Park et al.

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