Design of provably correct storage arrays

Details Design of provably correct storage arrays Design of provably correct storage arrays

1997-07-23

1999-11-30

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

36523008, G11C 700

Patent

active

059954256

ABSTRACT:
A hardware design technique allows checking of design system language (DSL) specification of an element and schematics of large macros with embedded arrays and registers. The hardware organization reduces CPU time for logical verification by exponential order of magnitude without blowing up a verification process or logic simulation. The hardware organization consists of horizontal word level rather than bit level. Using the elimination process for elements which are difficult to be extracted in Boolean form the logic around and inside a memory structure can be verified. The resultant register array hardware organization can be verified to all pins and nets up to the storage element.

REFERENCES:
patent: 5315178 (1994-05-01), Snider

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