Dense EPROM having serially coupled floating gate transistors

Details Dense EPROM having serially coupled floating gate transistors Dense EPROM having serially coupled floating gate transistors

1987-12-14

1990-06-12

Gossage, Glenn A.

Static information storage and retrieval

Read/write circuit

Signals

365185, 365204, 357 235, G11C 700

Patent

active

049339044

ABSTRACT:
A compact memory has a plurality of memory cells that are serially coupled. The plurality of cells are capacitively coupled to a substrate and directly coupled to switching circuits at both of its ends, which can disconnect the plurality of cells from a bit line at one end and a ground bus at the other end. An inhibit operation comprises precharging an array of pluralities of cells and the discharging of a selected plurality of cells. A WRITE operation comprises turning ON non-selected cells and then applying a programming voltage to a selected cell.

REFERENCES:
patent: 4099196 (1978-07-01), Simko
patent: 4150389 (1979-04-01), Roessler
patent: 4185319 (1980-01-01), Stewart
patent: 4442447 (1984-04-01), Ipri et al.
patent: 4467453 (1984-08-01), Chiu et al.
patent: 4495427 (1985-01-01), Cartwright, Jr.
patent: 4500975 (1985-02-01), Shirato
patent: 4580247 (1986-04-01), Adam
Yaron et al., "16K E.sup.2 PROM With New Array Architecture", Electronic Engineering, vol. 54, No. 666, Jun. 1982, pp. 35-47.

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