Destructive read type memory circuit, restoring circuit for...

Details Destructive read type memory circuit, restoring circuit for... Destructive read type memory circuit, restoring circuit for...

1999-03-26

2001-03-20

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S230060

Reexamination Certificate

active

06205076

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a destructive read type memory circuit, a restoring circuit for the same, a sense amplifier, and a semiconductor device including any one of the same.
2. Description of the Related Art
With increasing in the operation frequency of microprocessor, improving in the data transfer rate of memory device is required.
FIG. 33
shows a circuit connected to a bit line pair of a prior art DRAM.
A pair of complementary bit lines BL
1
and *BL
1
are, respectively, connected through transfer gates
10
and
11
to sense amplifier side wirings SA and *SA. A number of memory cells are connected to each of the bit lines BL
1
and *BL
1
, and in
FIG. 33
, only memory cells
12
and
13
are illustrated. A precharge circuit
14
with an equalizer and a CMOS sense amplifier
15
are connected between the wirings SA and *SA. The wiring SA is connected to a data bus line DB via a column gate
16
, and the wiring *SA is connected to a data bus line *DB via a column gate
17
.
FIG. 34
shows a read operation of the circuit in
FIG. 33
in a case where both of a cell plate potential Vcp at one end of a capacitor
121
of a memory cell
12
and a precharge potential of the bit lines BL
1
and *BL
1
are Vii/2.
In the initial state, the transfer gates
10
and
11
are on, the bit lines BL
1
and *BL
1
and the wirings SA and *SA are precharged to the potential Vii/2, and drive signals PSA and NSA of the CMOS sense amplifier
15
are at the potential of Vii/2, wherein a precharge signal PR is set to low, thereby NMOS transistors
141
through
143
are all off.
In this state, the row address is changed to raise the potential of the word line WL
1
, whereby the transfer gate
122
of the memory cell
12
is turned on, and a small potential difference arises between the bit lines BL
1
and *BL
1
by movement of electric charge between the capacitor
121
and the bit line BL
1
.
Next, the drive signal PSA is made to a potential Vii and the drive signal NSA is made to a potential Vss, whereby the CMOS sense amplifier
15
is activated and the small potential difference between the wirings SA and *SA is amplified.
Next, a column selection signal CL
1
is made high, and the column gates
16
and
17
are turned on, whereby data is read out onto the data bus lines DB and *DB.
The potential Vc of the capacitor
121
changes as shown with a dashed line in FIG.
34
. The rise of the potential Vc is gentle because of a time constant &tgr;=(resistances of the bit line BL
1
and transfer gate
122
)×(Capacitances of the capacitor
121
and bit line BL
1
). Time is denoted as t, and Vc is roughly expressed by Vc=Vii{1−0.5EXP(−t/&tgr;)}. For example, when Vii=2.4 V and Vss=0 V, it is necessary to fall down potential of a word line WL
1
after waiting until Vc becomes 2.35 V in order to rewrite data in the memory cell
12
. The time of restoring from the fall of the column selection signal CL
1
to the beginning of the fall of the word line WL
1
is about 20 ns.
After the potential of the word line WL
1
have fallen, the potential of the drive signals PSA and NSA is made at a potential of Vii/2, and the precharge signal PR is made high, whereby the bit lines BL
1
and *BL
1
are precharged to the potential Vii/2.
The row cycle time from the transition of row address to the completion of the precharge is about 40 ns.
Since data of the memory cells connected to the other bit lines (not illustrated) are read out on the respective bit line pairs at the same time if the word line WL
1
is selected, the data transfer is carried out at a high rate in a burst mode in which a column address is changed with the same row address, whereby the restoring time rate becomes rather small. Further, in a multi-bank type DRAM, in a case where data are accessed with the banks alternately changed, since the banks are changed when performing a restoring, the restoring time is concealed.
However, even in a multi-bank type DRAM, in random accesses wherein row addresses are frequently changed in the same bank, the data transfer ability is remarkably decreased by the restoring times.
Further, due to the following reasons, the access time from the potential rise of the word line WL
1
to a reading of data out of a memory device is lengthened.
(1) The CMOS sense amplifier
15
can not be activated to prevent an erroneous operation during the time from turning on of the transfer gate
122
to getting small potential difference of about 200 mV between the bit lines BL
1
and *BL
1
by movement of electric charge between the capacitor
121
and the bit line BL
1
. The time is comparatively long due to parasitic capacity and resistance of the bit line and transfer gate
122
.
(2) The size of transistors
151
through
154
of the CMOS sense amplifier
15
is greater by several times than that of transistors of the transfer gate
10
, etc., in order to prevent erroneous operations by decreasing characteristic variations resulting from process dispersion. Thereby, the gate capacities of the transistors
151
through
154
are comparatively great, and the activation time until the potential of the drive signal PSA becomes to Vii from Vii/2 and until the potential of the drive signal NSA becomes to Vss from Vii/2 is made long. Further, since sense amplifiers connected to respective bit line pairs, for example, 1024 bit line pairs, are simultaneously activated, the activation time is made still longer.
(3) Since the potential difference between the wirings SA and *SA is temporarily decreased as shown in
FIG. 34
when the column gates
16
and
17
are turned on, the column gates
16
and
17
are not able to be turned on until the potential difference becomes a certain value, in order to prevent erroneous operations of the CMOS sense amplifier
15
.
These problems decrease by employing a direct sensing system. However, since the amplification factor of the direct sensing system is smaller than in a case where a CMOS sense amplifier is used, the data access time can not be sufficiently shortened. Further, the above-described problem (2) can not be solved even if both the direct sensing system and CMOS sense amplifier are concurrently employed.
SUMMARY OF THE INVENTION
In view of the above-described problems, it is an object of the present invention to provide a destructive read type memory circuit, a restoring circuit, and a semiconductor device, which are able to shorten a row cycle time by omitting a restoring operation.
It is another object of the present invention to provide a sense amplifier circuit, a memory device and a semiconductor device including the same, which are able to shorten a row cycle time by adding a direct sensing function to the sense amplifier circuit.
In the 1st aspect of the present invention, there is provided a destructive read type memory circuit comprising: a memory cell array having a plurality of memory cells each of which is selected by a row address; a buffer memory cell; a restoring address register; and a control circuit for storing a present row address into the restoring address register, storing a content of the selected memory cell into the buffer memory cell, completing an access to the selected memory cell with a destructed content without restoring to the selected memory cell, and restoring in a free time the content of the stored buffer memory cell into the memory cell addressed by the content held in the restoring address register.
With the 1st aspect of the present invention, since restoring operation is omitted from data access operation and the content of the buffer memory cell is restored in the memory cell addressed by the contents held in the register in free time, for example, in a period of time during which a memory cell block, bank or chip is not selected, or in a period of refreshing time, the row cycle can be shortened, and particularly the data transfer rate can be improved in a random access where row addresses are frequently changed in the same memory b

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