Delayed bitline leakage compensation circuit for memory devices

Details Delayed bitline leakage compensation circuit for memory devices Delayed bitline leakage compensation circuit for memory devices

2006-08-01

2006-08-01

Nguyen, Tuan T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S204000, C365S207000, C365S189080

Reexamination Certificate

active

07085184

ABSTRACT:
A delayed bitline leakage compensation circuit for memory devices is disclosed. The delayed bitline leakage compensation circuit includes a bitline leakage model circuit for modeling discharge of a bitline by leakage current in a read operation. It further has a delayed charge signal generator for generating a delayed charge signal in response to the bitline leakage model circuit discharging to approximately a discharge threshold. The delayed charge signal generator is deactivated if the bitline is discharged by a selected memory cell. Moreover, the delayed bitline leakage compensation circuit includes a delayed charge circuit for charging the bitline in response to the delayed charge signal.

REFERENCES:
patent: 6160748 (2000-12-01), Kumar
patent: 6501687 (2002-12-01), Choi
patent: 6801463 (2004-10-01), Khellah et al.

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