Circuit structure having distributed registers with self-timed r
Circuit technique for column redundancy fuse latches
Circuit that prevents illegal transformation of data in a...
Circuit using a shared delay locked loop (DLL) and method...
Circuit which provides power on reset disable during a test mode
Circuit with a memory array and a reference level generator...
Circuit, system and method for executing a refresh in an...
Circuital structure for reading data in a non-volatile...
Circuitry and method for discharging a drain of a cell of a non-
Circuitry and method for indicating a memory
Circuitry and method for programming and erasing a non-volatile
Circuitry and methodology to test single bit failures of integra
Circuitry and methods for dynamically sensing of data in a stati
Circuitry and methods for efficient FIFO memory
Circuitry for a programmable element
Circuitry for a programmable element
Circuitry for a programmable element
Circuitry for reading from and writing to memory cells
Circuitry for reading phase change memory cells having a...
Circuitry for reducing parasitic coupling in core memory