Sensing architecture with decreased precharge voltage levels

Sensing circuit for a semiconductor memory

Sensing circuit for single bit-line semiconductor memory device

Serial access memory comprising disconnecting circuit between se

Series read-only-memory having capacitive bootstrap precharging

Signal transmission circuit and semiconductor memory using...

Signal transmission circuit and semiconductor memory using...

Simulated DRAM memory bit line/bit line for circuit timing and v

Single-ended sensing using global bit lines for dram

SRAM bit-line reduction

Stable memory cell read

Staggered bitline precharge scheme

Standby current reduction circuit applied in DRAM

State detection for storage cells

Static memory circuit

Static memory device

Static memory using a MIS field effect transistor

Static memory with pull-up circuit for pulling-up a potential on

Static RAM having a precharge operation which exhibits reduced h

Static random access memory