Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
2005-06-21
2005-06-21
Lebentritt, Michael S. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Precharge
C365S154000, C365S156000
Reexamination Certificate
active
06909652
ABSTRACT:
A SRAM with reduced subthreshold leakage current, the SRAM including a pMOSFET with its gate at VSSand its source at VCC, and a diode-connected pMOSFET with its source at VCC, where the drains of the pMOSFET and the diode-connected pMOSFET are connected together to provide a voltage VCCL, where VSS<VCCL<VCC. The beta of the diode-connected pMOSFET is substantially larger than the beta of the pMOSFET. The wordline associated with each memory cell is driven to a voltage −VEEduring a read operation, where −VEE<VSSand VEE≦VCC−VCCL. Each memory cell has cross-coupled inverters to store a data bit, where the cross-coupled inverters have pMOSFETs with their sources at VCCL.
REFERENCES:
patent: 6608786 (2003-08-01), Somasekhar et al.
patent: 6724649 (2004-04-01), Ye et al.
patent: 2004/0076059 (2004-04-01), Khellah et al.
Agawa, Ken'ichi et al., “A Bit-Line Leakage Compensation Scheme for Low-Voltage SRAM's,” 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 70-71, Jun. 2000.
De Vivek K.
Khellah Muhammad M.
Somasekhar Dinesh
Ye Yibin
Huter Jeffrey B.
Le Toan
Lebentritt Michael S.
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