Sensing circuit for a semiconductor memory

Details Sensing circuit for a semiconductor memory Sensing circuit for a semiconductor memory

2007-09-18

2007-09-18

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Precharge

C365S196000, C365S207000

Reexamination Certificate

active

10913128

ABSTRACT:
A sensing circuit for a semiconductor memory comprising a circuit branch intended to be electrically coupled to a memory bit line having connected thereto a memory cell to be sensed. A bit line precharge circuit is provided, for precharging the memory bit line to a predetermined potential in a precharge phase of a memory cell sensing operation. An evaluation circuit is associated with the memory bit line for evaluating an electric quantity developing on the memory bit line during an evaluation phase of the memory cell sensing operation; the electric quantity that develops on the memory bit line is indicative of an information content of the memory cell. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, so that the predetermined bit line potential is reached irrespective of a memory bit line initial potential at the beginning of the precharge phase. The bit line precharge circuit is adapted to both charging and discharging the memory bit line, depending on a difference between a memory bit line potential and the predetermined bit line potential. At least the precharge circuit includes a precharge negative feedback control loop, for controlling the memory bit line potential during the precharge phase. A same circuit element is provided that controls the memory bit line potential during the precharge phase and evaluates the electric quantity during the evaluation phase of the memory cell sensing operation.

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Partial European Search Report, EP03017939, Jan. 21, 2004.
Chun, Jino, et al., A 1.2 ns GaAs 4K Read Only Memory, IEEE, pp. 83-86, Nov. 1988.

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