5-Transistor memory cell which can be reliably read and written
5-transistor memory cell with known state on power-up
Active pull-up circuit
Active refresh circuit for dynamic MOS circuits
Adaptive precharge management for synchronous DRAM
Address decoding
Adjustable pre-charge in a memory
Apparatus and method for a current limiting bleeder device...
Apparatus and method for a high-speed memory
Apparatus and method for a memory storage cell leakage...
Apparatus and method for a memory storage cell leakage...
Apparatus and method for adjusting and maintaining a bitline pre
Apparatus and method for encoding auto-precharge
Apparatus and method for increasing data line noise tolerance
Apparatus and method for increasing test flexibility of a memory
Apparatus and method of reducing the pre-charge time of bit...
Apparatus and structure for rapid enablement
Apparatus and structure for rapid enablement
Apparatus for and method of current leakage reduction in...
Apparatus for increasing pulldown rate of a bitline in a...