Simulated DRAM memory bit line/bit line for circuit timing and v

Details Simulated DRAM memory bit line/bit line for circuit timing and v Simulated DRAM memory bit line/bit line for circuit timing and v

1996-12-03

1998-10-27

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Precharge

365205, G11C 700

Patent

active

058286098

ABSTRACT:
The voltages on the high voltage rails of sense amplifiers in dynamic random access memories are controlled during turn-on of the sense amplifiers to remain approximately at the voltage of the voltage source internal to the integrated circuit chip by connecting a voltage source external to the chip to the high voltage rails until the voltages on the rails equal the voltage from the chip's internal voltage source at which time the external voltage source is disconnected.

REFERENCES:
patent: 5262999 (1993-11-01), Etoh et al.
patent: 5627789 (1997-05-01), Kalb, Jr.
patent: 5636774 (1997-06-01), Rao

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