Static information storage and retrieval – Read/write circuit – Precharge
Reexamination Certificate
1999-10-25
2001-02-06
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Precharge
C365S208000, C365S230060
Reexamination Certificate
active
06185140
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to digital memories and more particularly to methods and apparatus for reading data from a digital memory.
2. Description of the Related Art
FIG. 1
is a circuit diagram of a prior art digital memory sensing architecture. As shown, a memory
10
comprises a plurality of memory cells
12
in a row by column format. Each of a plurality of read bitlines
14
(where there is one read bitline per column) is coupled to a column multiplexer
16
which selects a desired bitline and provides it to a sense amplifier
18
, which senses the value of the bitline (1 or 0) and provides the corresponding output. In a memory implemented with MOS technology, before a read is initiated, the bitlines
14
are precharged to a supply voltage less the threshold voltage V
tn
of a MOS transistor. Also, the input to the sense amplifier
18
is precharged to the supply voltage.
Each of the bit lines
14
such as bit line
14
a
has an associated n-type precharge transistor
20
, that receives a precharge signal. The precharge signal turns on the precharge transistor
20
, thus bringing the bit line
14
a
to the supply voltage (V
dd
) less the transistor threshold voltage (V
tn
).
A sense amplifier precharge circuit comprises a p-channel transistor
24
whose gate is coupled to the output of an invertor
21
. The sense amplifier precharge circuit serves to precharge the sense amplifier input node to V
dd
. In particular, the invertor
21
receives the precharge signal at its input and thus provides a low output when the precharge signal goes high. Thus, when the output of the invertor
21
goes low, the p-channel
24
pulls up the sense amplifier input node to V
dd
.
It would be desirable to have a sensing architecture that has faster read access but less power consumption than the circuit shown in FIG.
1
.
SUMMARY OF THE INVENTION
According to the present invention, bitlines may be precharged to the supply voltage (V
dd
) less a multiple of the transistor threshold voltage (V
tn
), where the multiple is greater than or equal to 2. By precharging to a lower voltage, power consumption is reduced and memory speed is increased.
According to an embodiment of the present invention, the above described precharge scheme is implemented with a circuit that comprises a plurality of read bitlines, a bitline precharge circuit, a column select circuit and a sense amplifier precharge circuit. A bitline precharge circuit establishes the precharge voltage at a first node on a first one of the plurality of bitlines. The bitline precharge circuit comprises a first n-type transistor with a drain coupled to receive a power supply signal at voltage V
dd
and a gate coupled to receive a precharge signal. The bitline precharge circuit further comprises a second n-type transistor with a drain and gate coupled to the source of the first n-type transistor wherein the source of the second n-type transistor is coupled to the first node.
The column select circuit comprises a third n-type transistor with a drain coupled to a sense amplifier input node and a gate coupled to receive a column select signal. The column select circuit further comprises a fourth n-type transistor with a drain and gate coupled to the source of the third n-type transistor wherein the source of the second n-type transistor is coupled to the first node. The sense amplifier precharge circuit comprises a p-type transistor with a source coupled to receive the power supply signal at voltage V
dd
, a gate coupled to receive the inverse of the precharge control signal, and a drain coupled to the sense amplifier input node. The first, second, third and fourth n-type transistors have an identical threshold voltage V
tn
.
REFERENCES:
patent: 6023436 (2000-02-01), Han
patent: 6026035 (2000-02-01), Kim
LSI Logic Corporation
Nelms David
Yoha Connie C.
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