Staggered bitline precharge scheme

Details Staggered bitline precharge scheme Staggered bitline precharge scheme

1997-12-22

2000-02-08

Nelms, David

Static information storage and retrieval

Read/write circuit

Precharge

365233, G11C 700

Patent

active

060234350

ABSTRACT:
A circuit and method for staggering a bitline precharge between particular sections of a memory array. The present invention may be implemented in memories having increasing depths to reduce unacceptably high precharge current requirements associated with high bitline loads. Since the particular memory sections of the memory array are turned on independently, the peak current necessary to charge the particular bitlines is limited. The present invention may be implemented in logic and may therefore be less sensitive to process and temperature variations.

REFERENCES:
patent: 5027326 (1991-06-01), Jones
patent: 5222047 (1993-06-01), Matsuda et al.
patent: 5546347 (1996-08-01), Ko et al.
patent: 5636174 (1997-06-01), Rao
patent: 5729498 (1998-03-01), Yih et al.
patent: 5745421 (1998-04-01), Pham et al.

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