Series read-only-memory having capacitive bootstrap precharging

Details Series read-only-memory having capacitive bootstrap precharging Series read-only-memory having capacitive bootstrap precharging

1983-01-24

1986-02-11

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Precharge

365104, G11C 1140, G11C 1700

Patent

active

045702390

ABSTRACT:
A read-only-memory (ROM) having a plurality of enhancement and depletion transistors selectively arranged in an array with the gates of the transistors in each row connected in common to form word lines, and the current paths of the transistors in each column connected in series to form bit lines. The word lines are precharged and then allowed to float. The bit lines are then precharged, bootstrapping the word lines above the precharge level. A selected one of the word lines is thereafter discharged before one end of each of the bit lines is connected to ground. A selected bit line will either remain precharged or be discharged depending upon the type of transistor at the intersection of the selected word and bit lines.

REFERENCES:
patent: 3611437 (1971-10-01), Varadi
patent: 4142176 (1979-02-01), Dozier
patent: 4183093 (1980-01-01), Kawagoe
patent: 4318014 (1982-03-01), McAlister et al.
patent: 4404654 (1983-09-01), Kamuro et al.
patent: 4485460 (1984-11-01), Stambaugh
Kawagoe, "Minimum Size ROM Structure Compatible with Silicon Gate E/D MOS LSI", IEEE Journal of Solid State Circuits, vol. SC-11, No. 3, Jun. 1976, pp. 360-364.
Lin, "A 4 .mu.m NMOS NAND Structure PLA ", IEEE Journal of Solid State Circuits, vol. SC-16, No. 2, Apr. 1981, pp. 103-107.

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