Standby current reduction circuit applied in DRAM

Details Standby current reduction circuit applied in DRAM Standby current reduction circuit applied in DRAM

2002-06-19

2004-08-10

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S190000, C365S205000, C365S207000, C365S208000

Reexamination Certificate

active

06775194

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention related to a circuit for reducing the leakage current of DRAM, more particularly to a circuit for reducing the short DC standby current between the bit line and the word line of DRAM.
2. Background of the Invention
In the manufacturing process of DRAM, a short circuit between the bit line and the word line sometimes occurs and causes a leakage current and affect the product yield.
One of the solution for the above-mentioned problem is disclosed in U.S. Pat. No. 5,499,211, entitled “BIT-LINE PRE-CHARGE CURRENT LIMITER FOR CMOS DYNAMIC MEMORIES.” As shown in
FIG. 1
, a conventional circuit
10
comprises a word line
12
, a pair of complementary bit lines
13
, a pre-charge equalizing circuit
14
and a current-limiting means
11
. In prior art, in order to prevent an excess leakage current caused by the short circuit between the bit line (BL) and the word line (WL), a current-limiting means
11
, such as a depletion NMOS, is added between a source of pre-charge voltage (VBLEQ)
15
and the pair of complementary bit lines
13
so as to limit the maximum leakage current when the short circuit between the bit line and the word line occurs.
Generally, the word line voltage (V
WL
) is 0 volt in the standby mode, but the bit line voltage is larger than 0 volt. Thus, a leakage current path will be formed in the standby mode. The leakage current will flow from BLEQ, BL, WL to the ground. In other words, the conventional method cannot effectively reduce the leakage current when the short circuit between the bit line and the word line occurs. For the current application in the product for low power DRAM, the leakage current is still too large to satisfy the market requirement.
Regarding the problems in the prior art, the present invention provides an innovative standby current reduction circuit for the DRAM to overcome the above-mentioned disadvantages.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a standby current reduction circuit for DRAM, which is suitable for the application requirement in a low power DRAM.
To this end, the present invention discloses a standby current reduction circuit for DRAM, which adds a pre-charge circuit between a pair of complementary bit lines of DRAM. The pre-charge circuit comprises a plurality of transistors in parallel or serial connection, which can generate a larger pre-charge current in an operating mode so as to relatively reduce the size of the current-limiting means and the resulting pre-charge current. Because the leakage current caused by the short circuit between the pair of complementary bit lines and the word line of DRAM usually comes from the pre-charge current of the current-limiting means, the present invention can reduce the standby current caused by the short circuit between the bit lines and the word line.
The standby current reduction circuit for DRAM according to the present invention comprises a pre-charge circuit and a current-limiting means. The pre-charge circuit provides a pre-charge current to the pair of complementary bit lines of DRAM only in the operating mode. The current-limiting means provides only a small pre-charge current to the pair of complementary bit lines of DRAM. With the pre-charge current provided by the pre-charge circuit, it can reduce the pre-charge current required by the current-limiting means to supply, and further reduce the leakage current forming in the standby mode due to short circuit between the pair of complementary bit lines and the word line of DRAM.


REFERENCES:
patent: 5499211 (1996-03-01), Kirihata et al.
patent: 6144599 (2000-11-01), Akita et al.

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