Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1991-11-12
1994-05-17
Gossage, Glenn
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
365185, 36518909, G11C 1606, G11C 1604
Patent
active
053134320
ABSTRACT:
A wordline-decode system of a nonvolatile memory array is split into three smaller decoding subsystems (a Read-Mode Decode Subsystem, a Program/Erase-Mode Decode Subsystem and a Segment-Select Decoder Subsystem). The segmented array has small bitline capacitance and requires few input connections to each decoding subsystem. The Read-Mode Decoder circuitry and the Program/Erase-Mode Decoder circuitry are separated, allowing the Read-Mode Decoder circuitry to be desired for high speed access and allowing the Program/Erase-Mode Decoder circuitry to be desired for high voltage operation. Buried-bitline segment-select transistors reduce the area required for those transistors. Erasing may be performed after first checking each row of a segment to determine the present of any over-erased cells. Programming may be performed by allowing the common source-column lines of the selected segment to float and by placing preselected voltages on the appropriate wordline and drain-column line.
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Ashmore, Jr. Benjamin H.
Gill Manzur
Lin Sung-Wei
McElroy David J.
Schreck John F.
Donaldson Richard L.
Gossage Glenn
Heiting Leo N.
Lindgren Theodore D.
Texas Instruments Incorporated
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