Scheme for eliminating page boundary limitation on initial acces

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

36523003, 3652385, 36518902, G11C 800

Patent

active

052854213

ABSTRACT:
In accordance with the present invention, a memory system capable of indefinite sequential access to a contiguous address space without stutter is provided. The memory system has a memory array divided into left and right halves, column and row decoders, memory output register banks A and B, and control logic. Upon initial access, the control logic determines whether, in the initial access data to be loaded in register banks A and B cross a row address boundary. If a row address boundary is crossed, data loaded into register bank A corresponds to data in one row in the right half of the memory array, and data in register bank B corresponds to data in the left half of the memory array in the next higher row. Thereafter, register banks A and B are interleaved for loading and output of memory data.

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