Segmented bus architecture for improving speed in integrated cir

Details Segmented bus architecture for improving speed in integrated cir Segmented bus architecture for improving speed in integrated cir

1993-06-29

1994-12-20

Yoo, Do Hyun

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365190, G11C 800

Patent

active

053750977

ABSTRACT:
A memory array wherein transfer bus length is reduced and segmented by arranging the column decoder select signals to run across the length of the word line to reduce the node capacitance seen by the corresponding memory cell. This transfer of low capacitance from the transfer bus, i.e., the critical path, to the select line, which is a non-critical path for speed, improves access speed.

REFERENCES:
patent: 5161121 (1992-11-01), Cho
patent: 5255228 (1993-10-01), Hatta et al.

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