Reducing power consumption in on-chip memory devices

Reducing read data strobe latency in a memory system

Reduction of capacitive effects in a semiconductor memory...

Reduction of fusible links and associated circuitry on...

Reduction of fusible links and associated circuitry on...

Reduction of fusible links and associated circuitry on...

Reduction of fusible links and associated circuitry on...

Reduction of the address pins of the integrated circuit

Redundancy architecture and method for non-volatile storage

Redundancy decoding circuit having automatic deselection

Redundancy decoding circuit using n-channel transistors

Redundancy semiconductor memory device which utilizes spare memo

Redundant form address decoder for memory system

Redundant memory arrangement providing simultaneous access

Redundant rows in integrated circuit memories

Redundant semiconductor memory device using a single now address

Reference voltage generator for CMOS memories

Refresh controller and address remapping circuit and method...

Refresh controller and address remapping circuit and method...

Refresh scheme for redundant word lines