Reduction of the address pins of the integrated circuit

Details Reduction of the address pins of the integrated circuit Reduction of the address pins of the integrated circuit

1996-07-15

1998-02-24

Nelms, David C.

Static information storage and retrieval

Addressing

Multiplexing

36523008, G10C 800

Patent

active

057217084

ABSTRACT:
A method is provided to input an address signal A.sub..o slashed., A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n to an integrated circuit. The integrated circuit includes an address decoder for providing a select signal. The method includes (1) inputting value of A.sub.1, A.sub.3 .about.A.sub.n to the address decoder during a first time interval, and, during the first time interval, an access-control signal being disabled to prohibit access operation by the integrated circuit; and (2) inputting value of A.sub.526, A.sub.2 .about.A.sub.n-1 to the address decoder during a second time interval, and, during the second time interval, the access-control signal being enabled to allow access operation corresponding to address value of A.sub.526, A.sub.1, A.sub.2 .about.A.sub.n-1, A.sub.n.

REFERENCES:
patent: 5371866 (1994-12-01), Cady

Affiliated with

Also associated with

Rating

Reduction of the address pins of the integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Reduction of the address pins of the integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reduction of the address pins of the integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1879049