Reducing read data strobe latency in a memory system

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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C365S193000, C365S159000

Reexamination Certificate

active

11193796

ABSTRACT:
A read activity detector circuit for use in a random access memory array includes a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals having a frequency that is substantially the same as a core reference clock and having different phases relative to one another. Each of the synchronizer circuits, in response to a first control signal presented thereto, generates an output signal having a rising edge or a falling edge which is substantially aligned to a rising edge or a falling edge of the reference clock signal corresponding thereto. The activity detector circuit further includes a controller operative to receive the respective output signals from the plurality of synchronizer circuits and to generate an output signal as a function thereof which is indicative of data to be read from the random access memory array.

REFERENCES:
patent: 5687203 (1997-11-01), Baba
patent: 6262611 (2001-07-01), Takeuchi
patent: 6373911 (2002-04-01), Tajima et al.
patent: 6777980 (2004-08-01), Young et al.
patent: 6950487 (2005-09-01), Lin et al.
patent: 7106655 (2006-09-01), Lee
patent: 2006/0202875 (2006-09-01), Fujisawa

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