Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2007-11-06
2007-11-06
Yoha, Connie C. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000, C365S159000
Reexamination Certificate
active
11193796
ABSTRACT:
A read activity detector circuit for use in a random access memory array includes a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals having a frequency that is substantially the same as a core reference clock and having different phases relative to one another. Each of the synchronizer circuits, in response to a first control signal presented thereto, generates an output signal having a rising edge or a falling edge which is substantially aligned to a rising edge or a falling edge of the reference clock signal corresponding thereto. The activity detector circuit further includes a controller operative to receive the respective output signals from the plurality of synchronizer circuits and to generate an output signal as a function thereof which is indicative of data to be read from the random access memory array.
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patent: 2006/0202875 (2006-09-01), Fujisawa
Liu Jin Song
Snodgrass Michael L.
Wang Jia Jing
Wang Tao
Zhu Wen
Agere Systems Inc.
Yoha Connie C.
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