Reduction of capacitive effects in a semiconductor memory...

Details Reduction of capacitive effects in a semiconductor memory... Reduction of capacitive effects in a semiconductor memory...

2005-07-12

2005-07-12

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Multiple port access

C365S063000

Reexamination Certificate

active

06917560

ABSTRACT:
A semiconductor memory device having a multiport memory includes a plurality of memory cells MC arranged in columns and rows, a plurality of first word lines WLA0-WLAn connected to a first port13a, and a plurality of second word lines WLB0-WLBn connected to a second port13b. Each of a plurality of first word lines WLA0-WLAn and each of a plurality of second word lines WLB0-WLBn are arranged alternately in a planar layout. A semiconductor memory device is thus obtained that allows a coupling noise between interconnections to be reduced without an increase in memory cell area.

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patent: 5877976 (1999-03-01), Lattimore et al.
patent: 5966317 (1999-10-01), O'Connor
patent: P2000-12704 (2000-01-01), None
patent: P2000-236029 (2000-08-01), None
patent: P2002-43441 (2002-02-01), None
patent: P2002-237539 (2002-08-01), None

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