Reference voltage generator for CMOS memories

Details Reference voltage generator for CMOS memories Reference voltage generator for CMOS memories

1988-12-14

1990-04-03

Fears, Terrell W.

Static information storage and retrieval

Addressing

Sync/clocking

36518909, 36523006, G11C 1300

Patent

active

049146343

ABSTRACT:
A semiconductor memory device including a pair of bit lines (BL, BL) having relatively high stray capacitances (C1, C2), a word line (WL), and a memory cell (MC1) connected to the bit lines and word line for selection by an address signal, and a restore circuit comprising a coupling/equalizing circuit (12) controlled by a BLR clock and a reference voltage generator (51) for quickly restoring the bit lines. The reference voltage generator (51) comprises both static and dynamic current sources. The static current source consists of a small N MOS transistor (N52) operating as a resistor load, while the dynamic current source consists of at least one small P MOS transistor (P'53, . . . ), connected in parallel with the N MOS transistor, and gated with a clock (BCC', . . . ) derived from the BLR clock, so that the P MOS transistor is turned ON during the restore time. An additional N device (N54) may be inserted between the reference line (RL) and ground (GND). The improved reference voltage of the present invention significantly reduces both consumed silicon area and restore time.

REFERENCES:
"A 4.5 ns 256 k CMOS SRAM with Tri-Level Word Line", Shinohara et al., 1985, IEEE International Solid-State Circuits Conference, pp. 62-63.

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