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Memory device having a plurality of cell array blocks including

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Memory device having a programmable register

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Memory device having a redundant memory block

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Memory device having a switchable clock output and method theref

Static information storage and retrieval – Addressing – Sync/clocking
Patent

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Memory device having a variable data output length

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Memory device having a variable data output length and a...

Static information storage and retrieval – Addressing – Sync/clocking
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Memory device having address generating circuit using phase...

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
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Memory device having asymmetrical CAS to data input/output mappi

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Memory device having components for transmitting and...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Memory device having data bus lines of uniform length

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Memory device having data paths permitting array/port...

Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate

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Memory device having delay locked loop

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Memory device having direct sense circuit

Static information storage and retrieval – Addressing – Plural blocks or banks
Patent

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Memory device having line address counter for making next...

Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate

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Memory device having multiple array structure for increased...

Static information storage and retrieval – Addressing – Plural blocks or banks
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Memory device having multiple power modes

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Memory device having open bit line structure and method of...

Static information storage and retrieval – Addressing – Plural blocks or banks
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Memory device having page copy mode

Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent

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Memory device having reduced power requirements and...

Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate

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Memory device having repeaters

Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
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