Memory device having multiple array structure for increased...

Details Memory device having multiple array structure for increased... Memory device having multiple array structure for increased...

2006-01-10

2006-01-10

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S233100, C365S230060

Reexamination Certificate

active

06985398

ABSTRACT:
One embodiment of the present invention provides a semiconductor memory including a bank of N memory arrays each having a corresponding array address, a bus providing an array address signal, a row address signal (RAS), and timing signals. The semiconductor memory further includes N tracking circuits each coupled between a different one of the N memory arrays and the bus. A first tracking circuit, in response to receiving a first array address for a first array via the array address signal and a first active state of the RAS, couples the first array to the bus such that only the first array responds to a first sequence of timing signals constituting a first bank transaction. A second tracking circuit, in response to receiving a second array address for a second array via the array address signal and a second active state of the RAS, couples the second array to the bus such that only the second array begins responding to second sequence of timing signals constituting a second bank transaction before the first bank transaction is complete.

REFERENCES:
patent: 5060145 (1991-10-01), Scheuneman et al.
patent: 5950219 (1999-09-01), Rao
patent: 5995438 (1999-11-01), Jeng et al.
patent: 6026466 (2000-02-01), Su et al.
patent: 6088293 (2000-07-01), Ho
patent: 6154414 (2000-11-01), Lee
patent: 6240046 (2001-05-01), Proebsting
patent: 6278648 (2001-08-01), Cowles et al.
patent: 6310814 (2001-10-01), Hampel et al.
patent: 6373752 (2002-04-01), Wright et al.
patent: 6449685 (2002-09-01), Leung
patent: 6529429 (2003-03-01), Cowles et al.
patent: 6567338 (2003-05-01), Mick
patent: 0 303 811 (1989-02-01), None

Affiliated with

Also associated with

Rating

Memory device having multiple array structure for increased... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device having multiple array structure for increased..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device having multiple array structure for increased... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3567738