Memory device having reduced power requirements and...

Details Memory device having reduced power requirements and... Memory device having reduced power requirements and...

1999-05-26

2001-01-30

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S203000, C365S233100, C365S230030

Reexamination Certificate

active

06181641

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits, and, more particularly, to a memory device.
BACKGROUND OF THE INVENTION
A static random access memory (SRAM) includes a memory array made up of memory cells in an arrangement of rows and columns. A single data bit in binary form can be stored in each memory cell. Each row includes a word line that interconnects memory cells on the row with a common control signal. Similarly, each column includes a complementary pair of bit lines coupled to at most one cell in each row. The word and bit lines can be controlled to individually access each memory cell of the memory array.
An asynchronous SRAM does not respond to a clock signal. Instead, an asynchronous SRAM responds to an address change. An address transition detect (ATD) circuit detects whether there has been a transition made on an address line. The ATD circuit indicates selection of a memory cell in a row different from a previously selected memory cell, and generates an address transition detect (ATD) pulse indicating an address change. Address transition detection is only necessary for a row address transition because precharging the bit lines is not necessary for a column address change. However, the ATD circuit may be applied to all addresses and/or control signals.
There is a bit line precharge circuit for each column of bit line pairs in the SRAM. Before data can be read out of the selected memory cell, the bit line pair associated with the selected memory cell must be precharged. Each time a subsequent memory cell on a new column is selected, the bit line pair for that corresponding memory cell must also be precharged before the data value can be read.
The bit line precharge circuits effectively connect the bit line pairs to a reference supply voltage. The reference supply voltage is typically midway between the high and low logic levels of the memory device. Conventionally, bit line pairs are precharged to one-half of the power supply voltage. If the bit line pairs were not precharged, a voltage difference present on the bit line pair may inadvertently discharge a value into the selected memory cell due to the high capacitive load caused by the other memory cells connected to the same bit line pair.
Currently, upon detection of a row address transition, the ATD pulse is globally applied to all the bit line precharge circuits
22
in an SRAM device
30
, as shown in FIG.
1
. An address input circuit
24
receives an address signal and provides the signal to the ATD circuit
20
. The ATD circuit
20
detects whether there has been a transition in the address signal from a previously received address signal, and if so, generates an ATD pulse. The ATD pulse is then applied globally to all of the bit line precharge circuits
22
.
The term global in this illustration means that all the bit line precharge circuits, collectively represented by the single block
22
, receive the ATD pulse for initiating precharging of their respective bit line pairs. As a result, all the bit line pairs are simultaneously precharged, which is typically to one-half of the power supply voltage. Simultaneously precharging all the bit line precharge circuits
22
causes the SRAM
30
to dissipate unnecessary power since data can only be read out of one memory cell at a time during a bit line precharge cycle. Another disadvantage of simultaneously precharging all the bit line precharge circuits
22
is that large voltage spikes occur, which tends to generate noise and cause the voltage level at the power pad to drop due to package (pin) inductance.
U.S. Pat. No. 4,969,125 to Caerula, et al., hereinafter referred to as the '125 Patent and is hereby incorporated by reference, discloses an SRAM device
39
having a segmented memory array that eliminates the problem of large current spikes by limiting the number of precharge circuits that are simultaneously precharged in response to the ATD pulse, as shown in FIG.
2
. The memory array
40
is divided into a plurality of memory array segments
42
a
-
42
n
, with each memory array segment containing a portion of all the bit line pairs. Each memory array segment
42
a
-
42
n
has a bit line precharge circuit
44
for precharging the bit line pairs associated therewith so that when the ATD circuit
46
generates the ATD pulse, only the bit line pairs associated with a selected memory array segment
42
a
are precharged. The segmented precharged driver
48
corresponding to the memory array segment
42
a
containing the memory cell to be read is selected for precharging the bit line precharged circuit
44
.
A drawback of the segmented SRAM device
39
disclosed in the '125 Patent is that the ATD pulse is still distributed to all the segmented precharged drivers
48
. This causes the SRAM
39
to dissipate unnecessary power since only one of the segmented precharge drivers
48
is actually selected for providing the ATD pulse to the memory array
42
a
. In addition, interfacing the ATD circuit
46
with each segmented precharge driver
48
causes the output of the ATD circuit
46
to see a large capacitive load. A large capacitive load slows down the rise and fall time of the ATD pulse and its propagation to the segmented precharge drivers
48
. Consequently, a delayed and loosely controlled ATD pulse slows down the access time of the SRAM device
39
.
To better control the ATD pulse in the '125 Patent, each address input has a true signal path and a complement signal path connected to respective address pulse generators. In other words, there is an address pulse generator for detecting a rising address transition and a separate address pulse generator for detecting a falling address transition.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is therefore an object of the present invention to reduce the power consumption of an SRAM device.
It is another object of the invention to provide a tightly controlled ATD pulse.
It is yet another object of the invention to provide a method for providing a localized ATD signal for precharging bit line pairs when reading a data value from a selected memory cell, which results in a reduction in the power consumption of the SRAM.
These and other objects, features and advantages in accordance with the present invention are provided by a memory device having a plurality of memory cells arranged in rows and columns and divided into a plurality of sub-arrays. A plurality of word lines connect rows of the memory cells, and a plurality of bit line pairs connect columns of the memory cells.
An ATD circuit detects an address transition for a selected memory cell and generates an ATD pulse in response thereto. A respective bit line precharge circuit is associated with each of the plurality of sub-arrays. The memory device includes an ATD distribution circuit for distributing the ATD pulse to only a selected sub-array containing the selected memory cell so as to activate only the bit line precharge circuit of the selected sub-array and not activate precharge circuits of other non-selected sub-arrays.
By activating the precharge circuit of only the selected sub-array, the active power of the memory device is reduced. When the memory device is included in an electronic device that operates from a battery powered source or is included in an electronic device which has limited ability to generate power, such as a satellite, for example, operation of the electronic device is prolonged.
The plurality of memory cells may be divided into N blocks of memory cells, and each block may then be further divided into M sub-arrays. The ATD distribution circuit thus includes a block distribution circuit for distributing the ATD pulse to only a selected block containing the selected sub-array, and a plurality of sub-array distribution circuits associated with each block for distributing the ATD pulse to the bit line precharge circuit associated with the selected memory cell in the selected sub-array. Since the ATD pulse is segmented, the resulting capacitive load to the output o

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