Memory device having data bus lines of uniform length

Static information storage and retrieval – Addressing – Plural blocks or banks

Patent

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Details

365 51, 365 63, G11C 800

Patent

active

060727446

ABSTRACT:
A memory device comprises data bus lines whose lengths and widths are uniform. The memory device can minimize the lengths of the data bus lines and reduce the time delay, the skew between signals and the current consumption by uniformly disposing the data bus lines to each block in each bank, wherein each bank contains a plurality of blocks therein.

REFERENCES:
patent: 5822257 (1998-10-01), Ogawa
patent: 5838627 (1998-11-01), Tomishima et al.
patent: 5867439 (1999-02-01), Asakura et al.

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