Memory device having delay locked loop

Details Memory device having delay locked loop Memory device having delay locked loop

2006-01-10

2006-01-10

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S230060

Reexamination Certificate

active

06985401

ABSTRACT:
A memory device minimizes the skew between an external clock and a DQS (or DQ) after the locking state by regulating a delay ratio of a replica delay model to compensate errors of process, temperature or voltage change. The memory device comprises: an input clock buffer for buffering an externally inputted external clock to generate an internal clock; a DLL for delaying the internal clock to synchronize a phase of the external clock with that of a DQS; an output clock buffer for buffering an output clock outputted from the DLL; and an output control unit for generating the DQS using a clock outputted from the output clock buffer. Here, the DLL comprises a replica delay model for modeling delay factors of the input clock buffer and other delay factors until the output clock outputted from the delay line is outputted to the outside of a chip, and for regulating a delay ratio in response to a plurality of control signals inputted externally in a test mode.

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