Memory device having direct sense circuit

Details Memory device having direct sense circuit Memory device having direct sense circuit

1999-06-15

2000-11-21

Nelms, David

Static information storage and retrieval

Addressing

Plural blocks or banks

365205, G11C 800

Patent

active

061512656

ABSTRACT:
A direct-sense activation circuit 20 is provided for a sense circuit row 12A. When a memory block 0 is activated, the direct-sense activation circuit 20 activates a direct-sense driving line in response to an activated read signal from the control circuit 18. The direct sense circuit is provided with a direct sense gate which is controlled by the voltage of a bit line and a column gate connected to the direct sense gate in series between the direct-sense driving line and a read-data bus line. A plurality of memory blocks are disposed in the direction perpendicular to the sense circuit row 12A, a column decoder 13 and a sense buffer circuit 15 are disposed so that these memory blocks are placed therebetween, and the word decoders are disposed on a side of the respective memory blocks.

REFERENCES:
patent: 5831919 (1998-11-01), Haunkness et al.
patent: 5881006 (1999-03-01), Yabe et al.
patent: 6026034 (2000-02-01), Suzuki et al.

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