Memory device having a switchable clock output and method theref

Details Memory device having a switchable clock output and method theref Memory device having a switchable clock output and method theref

1998-01-20

1999-12-14

Nelms, David

Static information storage and retrieval

Addressing

Sync/clocking

36518908, G11C 800

Patent

active

060026383

ABSTRACT:
A memory device with a switchable clock output. The memory device has a data pin, a clock input pin, and a clock output pin. The memory device is designed to be wired up to a plurality of other memory devices in a daisy chain manner. The clock input pin of the first memory device would be serially coupled to the first memory device. The clock output pin of each memory device would be serially coupled to the clock input pin of a directly successive memory device. The processor can then interrogate the first memory device for the identification information it contains. Once this information is obtained, the processor can issue a command to deactivate the first memory device from responding to bus commands, as well as to output the clock signal via the clock output pin to a directly successive memory device. The processor may then interrogate the next memory device.

REFERENCES:
patent: 5336950 (1994-08-01), Popli et al.
patent: 5544107 (1996-08-01), Hill

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