Memory device having asymmetrical CAS to data input/output mappi

Details Memory device having asymmetrical CAS to data input/output mappi Memory device having asymmetrical CAS to data input/output mappi

1993-12-06

1995-05-02

Fears, Terrell W.

Static information storage and retrieval

Addressing

Plural blocks or banks

365 63, G11C 1300

Patent

active

054126134

ABSTRACT:
A semiconductor memory chip architecture is described implementing of a multi-bit data control function which enables independent control of at least a plurality of data bits via a single control signal. A logically organized memory chip is organized as a 2.sup.n x 4 chip in which one control (CAS0) signal enables a single data bit and another control (CAS1) signal enables the remaining three data bits. By organizing data control on chips in this manner, it becomes possible to optimize design modules such that a minimum number of control signals are used.

REFERENCES:
patent: 3560940 (1971-02-01), Gaensslen
patent: 3675218 (1972-07-01), Sechler
patent: 5089993 (1992-02-01), Neal et al.

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