Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-07-26
2011-07-26
Le, Vu A (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S227000, C365S219000
Reexamination Certificate
active
07986584
ABSTRACT:
A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
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Barth Richard M.
Hampel Craig E.
Stark Donald C.
Tsern Ely K.
Le Vu A
Morgan & Lewis & Bockius, LLP
Rambus Inc.
Yang Han
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