LandOfFree - US Patents - Listing for Semiconductor device manufacturing: process,Making field effect device having pair of active regions...,Having insulated gate

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable pillars for contact formation

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable sidewall oxidation fabrication method for making a tr

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable sidewall spacer process for integrated circuits

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer and method of forming and using same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer and method of forming and using same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer and method of forming and using same

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer for symmetric and asymmetric Schottky...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer process for field effect transistor...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer technology for device tailoring

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer technology for reduced cost CMOS processing

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacer technology for reduced cost CMOS processing

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable spacers for improved array gapfill in high...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Disposable-spacer damascene-gate process for SUB 0.05 &mgr;m...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

DMOS architecture using low N-source dose co-driven with P-body

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

DMOS device structure, and related manufacturing process

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

DMOS device with sealed channel processing

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

DMOS fabrication process implemented with reduced number of mask

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

DMOS process module applicable to an E.sup.2 CMOS core process