Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-21
2001-06-12
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06245619
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to methods of fabricating metal oxide semiconductor field effect transistor (MOSFET) devices, and more particular to methods of fabricating MOSFET devices having a “Super-Halo” doping profile which provide excellent short-channel characteristics. The methods of the present invention are compatible with main stream CMOS (Complementary Metal Oxide Semiconductor) processes and are capable of forming very high performance MOSFETs of scaled-down size, in particular MOSFETs having a size that is smaller than 0.05 &mgr;m.
BACKGROUND OF THE INVENTION
In the field of MOSFET device manufacturing, it is well known that in order to scale MOSFET devices below 0.05 &mgr;m, the short channel effect problem has to be controlled with the use of a Super-Halo doping profile. This is described, for example, in Y. Taur, et al., “CMOS Devices Below 0.1 &mgr;m; How High Will Performance Go?”, 1997 IEDM Technical Digest, pp. 215-218. The Super-Halo doping consists of a highly non-uniform profile in both the vertical and the lateral directions. This non-uniform doping profile is seen, for example, in FIG.
1
A and simulated I
on
/I
off
characteristics (25° C.) of a 0.05 &mgr;m design with ±30% channel length tolerances are shown in FIG.
1
B. As is shown in
FIG. 1A
, pockets of high-doped regions are self-aligned to the gate and source/drain regions which help shield the gate-controlled depletion region from penetrating the source and drain fields. Superior short-channel, V
t
, control down to very short channel lengths (<0.035 &mgr;m) can be achieved with such an idealistic non-uniform doping profile.
To obtain Super-Halo doping profiles in MOSFETs, the thermal budget used to produce the structure, after halo implantation, has to be minimized, i.e., 1000° C., 1 sec. Utilizing a nitride disposable-spacer technique in processing MOSFET devices will result in minimizing the thermal budget used after halo implants. This prior art technique can be summarized as follows: After poly-gate definition and re-oxidation, nitride spacers (about 100 nm) are formed on the sidewalls of the polysilicon. Source, drain and gate implants are then performed followed by the required doping activation and drive-in anneals (1000° C., 5 seconds). The nitride spacers are subsequently removed (hence the name disposable-spacer) and the source and drain extensions (SDE) and the halo implants are performed. In order to activate the halo and SDE implants while minimizing any lateral (and vertical) diffusion, a very short channel anneal cycle (1000° C., 1 sec) is performed. This very short channel anneal cycle preserves the as-implanted abrupt profile of the halo doping obtaining the Super-Halo doping profile described hereinabove.
main problem with the above prior art technique arises from the way in which the nitride spacers are removed when applied to sub-0.05 &mgr;m MOSFET devices with very thin gate oxides (≦2 nm). The following two methods are currently employed in the prior art for removing nitride spacers: (1) A wet etch, using, for example, hot phosphoric acid; or (2) A dry etch using, for example, a Chemical Down-stream Etch (CDE) technique.
Both of the above etching processes do not exhibit good etch selectivity between nitride and doped oxide or doped silicon. An etch selectivity of 100:1 or greater (nitride to doped oxide or doped silicon) is required to remove the 100 nm nitride spacer without complete removal of the 2 nm oxide that is formed over the source and drain areas. The present etch selectivity of these techniques is in the order of 10:1.
This problem is clearly demonstrated in
FIGS. 2 and 3
. Specifically,
FIG. 2
shows a sketch of a prior art MOSFET structure before spacer etch. The oxide over the source and drain areas is of the same thickness as the gate oxide (≦2 nm). This oxide has also been doped during the source/drain implant step. Upon removing the disposable-nitride spacers, the oxide over the source and drain areas are etched and the source/drain areas are attacked resulting in the MOSFET structure (sketch) shown in FIG.
3
.
One obvious solution to the above problem is to increase the oxide thickness over the source and drain areas independent of the gate-oxide thickness (e.g., for the removal of 100 nm nitride spacer, greater than 10 nm of oxide is required over the source and drain areas). This may be done by using a thermal oxidation step after the nitride spacer formation to build-up the oxide over the source/drain areas to the required thickness. Unfortunately, such a technique would result in increased dopant diffusion from the source/drain regions to the thermally grown oxide increasing its etch rate to wet or CDE etches.
In view of the drawbacks with prior art MOSFET fabrication methods, there is a continued need to provide new and improved methods of fabricating MOSFET devices with a Super-Halo doping profile that provide excellent device short channel characteristics and enhanced device performance.
SUMMARY OF THE INVENTION
One object of the present invention is to provide methods of fabricating sub-0.05 &mgr;m MOSFET devices having a Super-Halo doping profile.
Another object of the present invention is to provide methods of fabricating scaled-down MOSFET devices (i.e., sub-0.05 &mgr;m) which have excellent device short channel characteristics and enhanced device performance.
A still further object of the present invention is to provide methods of fabricating sub-0.05 &mgr;m MOSFET devices in which the process technique employed in fabricating same is completely compatible with main stream CMOS processing techniques.
A yet further object of the present invention is to provide methods of fabricating sub-0.05 &mgr;m MOSFET devices wherein the oxide above the source/drain regions is not sufficiently removed and wherein the processing steps do not cause a sufficient increase in dopant diffusion from the source/drain regions to the oxide regions above the same. By preventing the increase in dopant diffusion from the source/drain regions into the oxide regions above the source/drain regions, the etch rate of the oxide region is not increased; therefore a structure such as shown in
FIG. 3
of the present application is not formed.
These and other objects and advantages can be achieved in the present invention by utilizing processing schemes wherein a damascene-gate technique is employed in fabricating MOSFET structures in which the oxide thickness above the source/drain regions are independent of the gate-oxide thickness and wherein a disposable-spacer technique is employed for the formation of a Super-Halo doping profile.
One method of the present invention which achieves the above objectives comprises the steps of:
(a) providing a structure having a gate stack formed on a surface of a substrate, said gate stack comprising at least a pad oxide layer formed on said surface of said and a first nitride layer formed on said pad oxide layer;
(b) forming at least one isolation trench region in said structure, said at least one isolation trench region being formed in said gate stack and a portion of said substrate;
(c) forming an oxide liner in said at least one isolation trench region;
(d) filling said at least one isolation trench region with a trench dielectric material;
(e) forming well implant regions in said substrate;
(f) forming a second nitride layer on said first nitride layer of said gate stack, wherein the total thickness of the first nitride layer and the second nitride layer is substantially equal to the thickness of a gate region to be formed subsequently therein;
(g) forming a gate hole in said first and second nitride layers stopping on said pad oxide layer;
(h) removing said pad oxide layer in said gate hole exposing a portion of said substrate;
(i) forming a thin oxide layer in said gate hole on said exposed portion of said substrate, said thin oxide layer having a thickness of 3 nm or less;
(j) filling said gate hole with polysilicon;
(k) removing said first and second nitride layers so as to expose
Boyd Diane Catherine
Hanafi Hussein Ibrahim
Natzle Wesley Charles
August Casey P.
Bowers Charles
International Business Machines - Corporation
Scully Scott Murphy & Presser
Thompson Craig
LandOfFree
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