Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-31
2001-08-28
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S303000, C438S305000
Reexamination Certificate
active
06281084
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a process of forming semiconductor devices and, more particularly, to modified gate conductor processing using disposable doped glass spacers for improved array gapfill in high density dynamic random access memories or embedded memories.
BACKGROUND OF THE INVENTION
The channel length of the dynamic random access memory (DRAM) transfer gate device continues to shrink aggressively. Conventional scaling techniques are limited in their applicability for the low leakage DRAM transfer device.
The present processing of DRAM structures in an array uses nitride spacers in a gate stack to provide margin for the borderless contacts. These same spacers in the support devices increase the distance of the P-FET extension and halo implants from gate polysilicon.
The top of the gate stack is more severely exposed to the borderless contact etch. Therefore, for improved borderless contact margin it is preferable to have a thicker borderless contact barrier at the top compared to the bottom. Divakaruni et al., U.S. patent application Ser. No. 09/325,942, filed Jun. 4, 1999 entitled “Modified Gate Conductor Processing for Poly Length Control In High Density DRAMs” describes a stack formed with tungsten silicide enclosed by nitride spacers before sidewall oxidation. The presence of these spacers ameliorates the need for additional large spacers in the array for borderless contact margin. However, the support P-FETs still need an offset from the support N-FETs for the extension and the halo implants. This offset currently is about 30 nm and the use of nitride spacers in the array at these dimensions uses up valuable space between the tightly packed gates and causes severe constraints for void free gapfill at low temperatures.
The present invention is directed to overcoming the problems discussed above in a novel and simple manner.
SUMMARY OF THE INVENTION
In accordance with the invention, a method utilizes disposable spacers to achieve improved gapfil in an array. The spacers define an offset between N-FET and P-FET extension and halo implants and are then removed.
Broadly, there is disclosed herein the process of forming a gate conductor for a semiconductor device. The process comprises the steps of providing a semiconductor substrate having a gate stack formed thereon, the gate stack including a sidewall. Dielectric spacers are formed on the gate conductor sidewalls, the dielectric spacers comprising an inner spacer and an outer spacer, the outer spacer being of a disposable material, such as doped glass or TEOS. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacers are then removed.
It is a feature of the invention that thickness of the outer spacer is greater than the inner spacer.
It is another feature of the invention that the outer spacer is selected from a group consisting of BSG, PSG, BPSG, FSG, F-BSG, ASG and TEOS.
It is a further feature of the invention that the forming step comprises depositing a first layer of dielectric material, typically SiN, over the semiconductor substrate and the gate stack, and then depositing a second layer of doped glass over the first layer. The dielectric material is selected from a group consisting of nitride and oxide. The forming step further comprises the step of etching horizontal surfaces of the first and second layers to form the dielectric spacers.
There is disclosed in accordance with another aspect of the invention the process of forming a gate conductor for a semiconductor device. The process comprises the steps of providing a semiconductor substrate having an oxide layer and a gate stack formed thereon. The gate stack includes a layer of polysilicon on the oxide layer, a conductor material layer on the polysilicon layer, and a nitride cap layer on the conductor material layer. A nitride prespacer surrounds at least part of the stack to define a gate conductor sidewall. Dielectric spacers are formed on the gate conductor sidewalls. The dielectric spacers comprise an inner spacer and an outer spacer. The outer spacer is of doped glass or TEOS material. Ions are implanted into the semiconductor substrate outwardly of the dielectric spacers. The outer spacer is then removed. Note that the inner spacer may then be etched and additional implants performed if necessary.
Further features and advantages of the invention will be readily apparent from the specification and from the drawing.
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Akatsu Hiroyuki
Divakaruni Ramachandra
Lee Gill Yong
Infineon Technologies Corporation
Lindsay Jr. Walter L.
Niebling John F.
Wood Phillips VanSanten Clark & Mortimer
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