DMOS fabrication process implemented with reduced number of mask

Details DMOS fabrication process implemented with reduced number of mask DMOS fabrication process implemented with reduced number of mask

1996-03-06

1997-09-16

Tsai, Jey

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 21265

Patent

active

056680260

ABSTRACT:
A new DMOS fabrication process is disclosed. The fabrication process includes the steps of (a) growing an oxide layer on the substrate; (b) applying a first mask to define an active area and for selectively patterning the oxide layer for keeping a plurality of source implant blocking stumps near a plurality source regions wherein the blocking stumps being formed with width greater than twice a diffusion length of a source dopant and with width less than twice a diffusion length of the body dopant whereby the body regions merging together in the body diffusion becoming a single body region underneath the blocking stumps; (c) applying a second mask for forming a plurality of gates covering a portion of areas between the blocking stumps defining an implant window; (d) implanting a body dopant through the implant window followed by a body diffusion for forming a body region underneath the blocking stumps; (e) implanting the source dopant through the implant window over the source implant blocking stumps following by a source diffusion for forming separate source regions underneath the blocking stumps; (f) depositing an insulating dielectric BPSG/PSG layer; (g) employing a contact mask for etching through the insulating dielectric BPSG/PSG layer and the source implant blocking stumps to define contact windows; (h) depositing a metal layer to form a contact layer through the contact window; and (i) patterning the metal layer with a metal contact to define a plurality of contacts whereby the transistor is fabricated with a four masks process.

REFERENCES:
patent: 4626293 (1986-12-01), Schols
patent: 4845051 (1989-07-01), Cogan et al.
patent: 4914058 (1990-04-01), Blanchard
patent: 5288653 (1994-02-01), Enjoh
patent: 5298442 (1994-03-01), Bulucea et al.
patent: 5567634 (1996-10-01), Herbert et al.

Affiliated with

Also associated with

Rating

DMOS fabrication process implemented with reduced number of mask does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DMOS fabrication process implemented with reduced number of mask, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DMOS fabrication process implemented with reduced number of mask will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-217701