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Technique for reducing parity bit-widths for check bit and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Technique for referencing failure information representative...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique for remote state notification and software fault...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique for sharing hot spare drives among multiple subsystems

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent

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Technique for sharing parity over multiple single-error...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Technique for synchronizing faults in a processor having a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique for synchronizing faults in a processor having a...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique for testability of semiconductor integrated circuit

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique for testing processor interrupt logic

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique for verifying a configuration of a storage...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique to decrease the exposure time of infrared imaging...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Technique to detect drive strength of input pin

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Technique to support pseudo-names

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Technique to test an integrated circuit using fewer pins

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Techniques for automatic eye-degradation testing of a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Techniques for automatic software error diagnostics

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Techniques for automatic software error diagnostics and...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Techniques for automatic software error diagnostics and...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Techniques for automatically tracking software errors

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Techniques for capturing signals at output pins in a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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