Technique for testing processor interrupt logic

Details Technique for testing processor interrupt logic Technique for testing processor interrupt logic

2006-01-31

2006-01-31

Baderman, Scott (Department: 2113)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C710S264000

Reexamination Certificate

active

06993685

ABSTRACT:
In a technique for testing processor interrupt logic, interrupts are sent to a microprocessor under test in a random order to test the processor interrupt logic of the microprocessor under test. The processor interrupt logic is considered to have failed the test if the microprocessor under test services a new interrupt having a priority level equal to or lower than a priority level of a previously received interrupt being serviced just prior to the receipt of the new interrupt. Furthermore, pseudo-masked interrupts are included in the interrupts being sent to the microprocessor under test. If a pseudo-masked interrupt is serviced by the microprocessor under test, the processor interrupt logic is considered to have failed the test. On the other hand, if the pseudo-masked interrupt is not serviced by the microprocessor under test, a lower (that is, soft) limit of the pseudo-masked interrupts is increased to that of the received pseudo-masked interrupt which has not been serviced by the microprocessor under test.

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IBM Tech. Disc. Bull., “Diagnostic Interrupt Logic Testing”, Oct. 1990, vol. 33, No. 5, pp. 80-81.

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