Technique for synchronizing faults in a processor having a...

Details Technique for synchronizing faults in a processor having a... Technique for synchronizing faults in a processor having a...

2007-01-02

2007-01-02

Le, Dieu-Minh (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C712S218000

Reexamination Certificate

active

10614215

ABSTRACT:
A computer processor includes a replay system to replay instructions which have not executed properly and a first event pipeline coupled to the replay system to process instructions including any replayed instructions. A second event pipeline is provided to perform additional processing on an instruction. The second event pipeline has an ability to detect one or more faults occurring therein. The processor also includes a synchronization circuit coupled between the first event pipeline and the second event pipeline to synchronize faults occurring in the second event pipeline to matching instruction entries in the first event pipeline.

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