Techniques for capturing signals at output pins in a...

Details Techniques for capturing signals at output pins in a... Techniques for capturing signals at output pins in a...

2008-07-29

2008-07-29

Louis-Jacques, Jacques (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S734000

Reexamination Certificate

active

07406642

ABSTRACT:
Techniques are provided for capturing external signals at output pins on a programmable logic integrated circuit (IC) during a boundary scan test. A JTAG sample signal is routed to an input/output block on a chip and active during a JTAG sampling phase. An input buffer coupled to an output pin is turned on during the JTAG sample phase. Logic gates enable the input buffer in response to the JTAG sample signal so that the input buffer can capture a signal on the pin. The input buffer is turned off after the JTAG sampling phase to conserve power. The output buffer coupled to the pin that receives the test signal is tristated to prevent contention during the JTAG sampling phase. The techniques of the present invention can be used to test board level interconnects in less time and are easy to implement.

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