Technique for reducing parity bit-widths for check bit and...

Details Technique for reducing parity bit-widths for check bit and... Technique for reducing parity bit-widths for check bit and...

2011-06-14

2011-06-14

Torres, Joseph D (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

07962837

ABSTRACT:
A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.

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Ghosh, S. et al.; “Selecting Error Correction Codes to Minimize Power in Memory Checker Circuits”; Journal of Low Power Electronics, vol. 1, 2005, pp. 26.
Ghosh, S. et al.; “Reducing Power Consumption in Memory ECC Checkers”, Proceedings of the IEEE International Test Conference (ITC-2004), Charlotte, NC, Oct. 2004, pp. 10.

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