Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent
1998-05-29
2000-10-17
Nguyen, Hoa
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
G01R 3128
Patent
active
061346861
ABSTRACT:
A method and apparatus comprising (i) a first circuit that may be configured to generate a first and second pulse in response to a reset signal, (ii) a latch circuit that may be configured to generate a first and second latch output in response to (a) the first and second pulses, (b) the reset signal and (c) an input signal and (iii) a third circuit that may be configured to generate a detect output in response to the first and second latch outputs. The detect output may be implemented as a trigger signal having an enabled state indicating a floating voltage is present on the input signal. The first and second latch outputs may be used to indicate the drive strength of the input signal. The enabled state of the detect output may have a floating state other than a standard logic "1" or logic "0".
REFERENCES:
patent: 5077521 (1991-12-01), Langford, II et al.
patent: 5198707 (1993-03-01), Nicolai
patent: 5491794 (1996-02-01), Wu
patent: 5942925 (1999-08-01), Stahl
Cypress Semiconductor Corp.
Maiorana P.C. Christopher P.
Nguyen Hoa
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