Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2005-11-22
2005-11-22
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S715000
Reexamination Certificate
active
06968490
ABSTRACT:
Embodiments of the invention relate to techniques for automatic degradation testing of a high-speed serial receiver. A transmitter manipulator couples to a transmitter of a serial interface circuit. The transmitter is coupled to the receiver of the serial interface circuit. The transmitter manipulator includes a storage to store one of current compensation values or impedance compensation values and sequencing logic to dynamically sequence the one of the current compensation values or impedance compensation values to the transmitter. The transmitter responsive to the dynamically sequenced one of the current or impedance compensation values generates a degraded test pattern signal to transmit to the receiver in order to test the receiver.
REFERENCES:
patent: 3737637 (1973-06-01), Frankeny et al.
patent: 3869580 (1975-03-01), Ragsdale
patent: 5734676 (1998-03-01), Dingsor
patent: 5751114 (1998-05-01), Dingsor
patent: 5761259 (1998-06-01), Dingsor
patent: 6215817 (2001-04-01), Kimura
patent: 6269482 (2001-07-01), Gershfeld
patent: 6301633 (2001-10-01), Chapman
patent: 6445718 (2002-09-01), Muto
patent: 6718296 (2004-04-01), Reynolds et al.
patent: 6777971 (2004-08-01), Kirloskar et al.
Levitan S. P., et al. Computer Aided Design for Free Space Optical Interconnected Systems, IEEE Lawers and Electro-Optics Society, 1999 Annual Meeting, Leos '99, Nov. 11, 1999, pp. 623-624, XP00282733, San Franscisco, CA.
Tahim, K. S., et al “A Radical Exploration Approach to Manufacturing Yield Estimation and Design Centering” IEEE Transactions on Circuits and Systems. vol. 26, No. 9, Sep. 1979 pp. 768-774, XP001181496 Sections I, II.
Buttle, K. et al. “A Multirate Transceiver IC for Four-Wire Full-Duplex Data Transmission” IEEE Journal of Solid-State Circuits, IEEE Inc. New York, vol. 26, No. 12, Dec. 1991, pp. 1928-1934, XP000272853 ISSN: 0018-9200 Fig. 3.
Haideh, K. et al., “A Highly Efficient CMOS Line Driver with 80-DB Linearty for ISDN U-Interface Applications” IEEE Journal of Solid-State Circuits, IEEE Inc. New York, vol. 27, No. 12, Dec. 1992, pp. 1723-1729, XP000329021 ISSN: 0018-9200 Fig. 1-3.
Bleakley Thomas E.
Tarango Tony M.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Ton David
LandOfFree
Techniques for automatic eye-degradation testing of a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Techniques for automatic eye-degradation testing of a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Techniques for automatic eye-degradation testing of a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3452829