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Method of testing circuit blocks of a programmable logic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing circuit blocks of a programmable logic device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing computer system with hard disk

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method of testing data paths in an electronic circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of testing detection and correction capabilities of...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Testing of error-check system
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Method of testing embedded memory array and embedded memory...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method of testing fiber channel ports in a storage server at...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method of testing logic devices

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of testing memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of testing memory operations employing self-repair circui

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Patent

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Method of testing memory with continuous, varying data

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of testing multi-core processors and multi-core processor

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent

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Method of testing multiple modules on an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing multiple modules on an integrated circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Method of testing random-access memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of testing semiconductor apparatus

Error detection/correction and fault detection/recovery – Pulse or data error handling – Skew detection correction
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Method of testing server side objects

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
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Method of testing the data exchange functionality of a memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Method of the ARQ type for a transmission method using...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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