Method of testing memory device

Details Method of testing memory device Method of testing memory device

2008-04-15

2008-04-15

Chase, Shelly (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S700000, C365S201000

Reexamination Certificate

active

10402181

ABSTRACT:
A test method of a memory device equipped with an internal signal generating circuit which generates an internal signal with a fixed cycle asynchronous with a signal from the outside is disclosed in which when an entry information is input, an entry circuit generates an output upon discrimination that said memory device is satisfying conditions for performing test, and when an output of the entry circuit is generated and a memory arrangement of the memory device is in a write enable state, a gate circuit generates an output to activate a buffer circuit, by which the internal signal is written to the memory arrangement by being connected to a data write input of the memory arrangement via the buffer circuit, then reading the written data to the outside from the memory arrangement, and performing the measurement related to the internal signal by detecting data change points.

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IBM Technical Disclosure Database, No. NN8006203. Memory Tester using Random Addresses and Random Data. vol. 23, issue 1, p. 203. Jun. 1980.
Wikipedia Online Encyclopedia. Phase Locked Loop. http://en.wikipedia.org/wiki/Phase-locked—loop.

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