Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-01-14
2000-10-17
Sheikh, Ayaz R.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
714 49, 714 39, 714 25, 714 31, 714724, G06F 1100
Patent
active
061346756
ABSTRACT:
A method of testing a multi-core processor that includes the steps of receiving a plurality of input signals from a plurality of processor cores (100), and producing an output signal corresponding to a disable state when at least two of the plurality of input signals represent a different logic value (106). A testing device (12) includes a multiplexer (40) responsive to a plurality of input signals (24, 26, 28, 30) from a plurality of processor cores (14, 16, 18, 20), and an output driver (48) responsive to the multiplexer (40). The output driver (48) produces an output signal (62) corresponding to a disable state when at least two of the plurality of input signals (24, 26, 28, 30) represent a different logic value.
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Miron Abramovici, et al., "Digital Systems Testing and Testable Design", Section 4.2 Fault Detection and Redundancy, published by IEEE Press, pp. 95-106.
Jean Frantz B.
King Robert L.
Motorola Inc.
Sheikh Ayaz R.
Toler Jeffrey G.
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