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Advanced bit fail map compression with fail signature analysis

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Advanced forward error correction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Data pulse evaluation/bit decision
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Algebraic construction of LDPC (Low Density Parity Check)...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Algebraic decoder and method for correcting an arbitrary...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Algebraic geometric code adapted to error bursts

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Algebraic low-density parity check code design for variable...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Algebraic soft decoding of reed-solomon codes

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Algorithm for a memory-based Viterbi decoder

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Algorithm for resynchronizing a bit-sliced crossbar

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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Algorithm pattern generator for testing a memory device and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Algorithm to test LPAR I/O subsystem's adherence to LPAR I/O...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Algorithmic pattern generator

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Algorithmic pattern generator for integrated circuit tester

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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Algorithmic test pattern generator, with built-in-self-test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Algorithmically programmable memory tester with history...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Algorithmically programmable memory tester with test sites...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Allocating data bursts and supporting hybrid auto...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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Allocation of sparing resources in a magnetoresistive...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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Almost full-scan BIST method and system having higher fault...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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Altering bit sequences to contain predetermined patterns

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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